The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for reducing particle contamination during substrate processing. The present invention is particularly useful for chemical vapor deposition processing, but may also be applied to plasma etching and other substrate processing techniques.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or "CVD". Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having metal layers.
One particular thermal CVD process that has been developed to deposit insulation films over metal layers at relatively low, nondamaging temperatures includes deposition of a silicon oxide layer from TEOS and ozone precursor gases. Such a TEOS/ozone silicon oxide film may be deposited under carefully controlled pressure conditions in the range of between about 100-700 torr, and is therefore commonly referred to as a subatmospheric CVD (SACVD) film. The high reactivity of TEOS with ozone reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such SACVD processes.
Another CVD method of depositing layers over metal layers at relatively low temperatures includes plasma enhanced CVD (PECVD) techniques. Plasma CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone proximate the substrate surface, thereby creating a plasma of highly-reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called "Moore's Law") which means that the number of devices which will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing 0.5 and even 0.35 micron feature size devices, and tomorrow's plants soon will be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, one issue that has become increasingly important is the ability of a deposited insulating layer to fill closely spaced gaps (referred to as a film's "gap fill" capability) such as those between adjacent metal lines. Because of their different, yet complimentary film characteristics, one process that has been used successfully to fill gaps up to an aspect ratio of 2.0 or higher, is the deposition of a three layer silicon oxide dielectric film in which a thin PECVD silicon oxide layer is deposited over stepped topography (such as adjacent metal lines) of a substrate, as an initial lining layer and diffusion barrier for an SACVD TEOS/ozone silicon oxide layer that fills in the gaps between the metal lines. A compressively stressed PECVD silicon oxide layer is then deposited over the SACVD layer prevent moisture absorbtion in the SACVD layer and to counteract the tensile stress of the SACVD layer ensuring that the film has a low compressive stress. The entire deposition sequence takes place in an in situ process.
Another concern in the manufacture of high density integrated circuits are contaminant particles. In particular, contaminant particles attach themselves to unpassivated elements of integrated circuit devices during fabrication, where they can create short circuits or cause reliability or other problems. Therefore, the contaminant particles ultimately reduce the yield of good dies on a conventional semiconductor wafer. Even worse, as feature sizes decrease, the influence of contaminant particles in the fabrication of integrated circuits becomes greater.
Accordingly, semiconductor equipment vendors and users, alike, often rely upon elaborate and expensive techniques to control potential sources of contaminant particles. Such techniques include the use of ultra-clean rooms, super automated handling equipment, and sophisticated process controls during the fabrication of integrated circuits to reduce the potential sources of contaminant particles. However, such techniques can only be of limited success because substantial amounts of contaminant particles in integrated circuit fabrication are actually derived from reactant by-products created when semiconductor wafers undergo processing.
These reactant by-products often attach themselves to interior surfaces of a process chamber and form into a contaminant residue layer. Typically, the contaminant residue layer is derived from by-products of reactant gases and other by-products already attached to interior surfaces of the process chamber. Portions of the contaminant residue layer can flake off and deposit onto unpassivated surfaces of the integrated circuit.
To prevent portions of the contaminant residue layer from damaging the integrated circuit, a variety of cleaning techniques have been used. Some of these cleaning techniques require separate process steps, which include machine shut-down and cleaning, after each deposition step. This is time consuming, expensive, and difficult to achieve. Additionally, when a processing machine is not operating, wafer throughput on the fabrication line drops, rendering the manufacturing process all the more expensive.
In another cleaning technique, referred to as plasma enhanced dry cleaning, an etchant gas, such as fluorine, is introduced into the chamber during a separate cleaning step. A plasma is formed from the etchant gas and constituents from the plasma react with and remove the deposited material from the chamber walls and other areas. Such cleaning procedures commonly need to be performed after every deposition run or after every several deposition runs to be effective in keeping the interior surfaces of the process chamber substantially free from contaminant residues and particles.
In the exemplary PECVD/SACVD/PECVD three layer film described above, a dry cleaning step may be performed after deposition of the SACVD layer to reduce particle contamination. That is, after deposition of the SACVD silicon oxide layer of the film, the wafer is removed without breaking vacuum seal and the chamber is evacuated to pump out remaining gases and loose particles. Next, a fluorine etch step is performed to clean the chamber and remove contaminants and other residue that has built up within the chamber. The etch step includes increasing chamber pressure during the etching process and reevacuating the chamber after completion of the process. Upon completion of the etch step, the wafer is loaded back into the chamber and deposition of the PECVD film is initiated.
Without such a dry clean step, particles tend to build up and collect on the chamber walls and in areas such as the perforated holes of the gas dispersion manifold after deposition of the SACVD layer. The particles built up within the perforated holes may be later forced out of the holes and deposited onto the wafer when the PECVD deposition gases are introduced into the evacuated chamber as described in more detail below. The use of a clean step between the SACVD and PECVD depositions, however, consumes processing time and reduces wafer throughput. Also, the clean step can, in itself, be a source of particle accumulation. Measurements show that particles which may cause contamination problems may build up during this process even in spite of the clean step between depositions. Thus, from the above it can be seen that new methods of reducing particle contamination are desirable.